1. Field of the Invention
This invention relates generally to matched capacitor arrays, and more particularly to a method of generating matched capacitor arrays for use in association with analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, programmable gain amplifiers, and the like.
2. Description of the Prior Art
Capacitors are used for input signal storage/gain in programmable gain amplifiers, A/D converters, D/A converters and the like where the input signal is analog in nature. Any error in the design or layout of the capacitor array affects the linearity performance of the respective circuit. This makes the capacitor array a critical component of the device.
A capacitor array is a set of capacitors placed in a particular fashion within a planar (e.g. XY) space. The capacitors in an array are divided into different groups that are related to one another by a defined ratio. A capacitor array is laid out as a set of unit capacitors as a first step towards improving the matching of the array.
Capacitor mismatch occurs as a result of processing errors such as patterning and etching variations. Some of these result in spatial variation of the capacitance value and other characteristics in random variation. Parasitic (unintentional) capacitance also must be matched for all the unit capacitors in the array, since capacitor mismatch directly affects the linearity performance of the design. The effects of spatial variation of capacitance can be minimized to a large extent by careful arrangement of the unit capacitors in a predetermined fashion. The foregoing factors make the layout of a capacitor array complicated wherein the criticality of the array layout increases as the resolution increases.
Layout cycle time of a capacitor array is generally about three weeks for the following reasons: 1) manual creation and integration of several tasks; 2) post layout error checking; 3) design rules differ from process to process, which prevents the user from reusing an existing array in some other process without modifying the layout; and 4) post processing and parasitic extraction for the array.
One example of systematic spatial variation regarding capacitance values is directed to variation of thick-oxide in a given area of silicon, that acts as di-electric for the capacitors. Unit capacitors belonging to a group should be distributed in a given area such as illustrated in FIG. 1, to cancel the mismatch and avoid this difficulty.
Metal layers are used to connect all of the top and bottom plates of capacitors within an array. Any overlap of these metal layers with themselves and other layers results in parasitic capacitance that adds to the absolute value of the unit capacitor. If the parasitic capacitance is not the same for all the unit capacitors, then there will be a mismatch between the capacitors. Since the top and bottom plate lines are very sensitive, any parasitic capacitance increase the chance of coupling between these lines and other lines which are noisy, thereby degrading the array performance. The foregoing difficulties can be overcome by minimizing the parasitics. Where the parasitics cannot be minimized or avoided, they should be the same for all unit capacitors. These requirements severely complicate the layout of a capacitor array.
Cycle time for completing a capacitor array layout is about three weeks, as stated herein before. It can be appreciated that three weeks is a very significant amount of time in the design cycle time of any project. This design cycle time is necessary for manual creation and integration of several tasks that include generation of the unit capacitor, placement of unit capacitors within an array, routing of bottom plate control lines, connection of bottom plates associated with all capacitors, top plate line connectivity, shielding for matching, and verification of layout for connectivity and process design rules. Quality checks for accuracy are also necessary.
Each unit capacitor in the array is unique since its capacitance value gets defined by its location in the array (due to the spatial variation effect). No layout verification tool can verify this since all unit capacitors are assumed to have the same value. This necessitates manual checking of the arrangement of the unit capacitors. Such manual checking is error prone and increases the cycle time.
Any layout modification(s) to an existing array is/are also very difficult. If a polygon in the layout needs to be modified, for example, then the full array needs to be modified to satisfy all the design rules of the new process.
As stated above, the array should be verified with the design for all connectivity subsequent to completion of layout work for the array that should be complete through all of the design rules defined for the process which also adds to the total cycle time. Further, detailed information regarding the parasitics of the array are very much necessary to analyze the linearity performance of the capacitor array. Generating this detailed parasitic information further adds to the time consuming cycle time.
In view of the foregoing, a need exists in the capacitor array generation art for an efficient and cost effective automated layout procedure to generate capacitor arrays that are analogous in nature.
The present invention is directed to a method of generating matched capacitor arrays for use in association with analog-to-digital (A/D) converters, digital-to-analog (D/A) converters, programmable gain amplifiers, and the like. The method provides correct by construction capacitor arrays within a short (optimal) design cycle time.
As used herein, the following words have the following meanings. The words xe2x80x9calgorithmic softwarexe2x80x9d mean an algorithmic program used to direct the processing of data by a computer or data processing device. The words xe2x80x9cdata processing devicexe2x80x9d as used herein refer to a CPU, DSP, microprocessor, micro-controller, or other like device and an interface system. The interface system provides access to the data processing device such that data could be entered and processed by the data processing device. The words xe2x80x9cdiscrete dataxe2x80x9d as used herein are interchangeable with xe2x80x9cdigitized dataxe2x80x9d and xe2x80x9cdigitized dataxe2x80x9d as used herein means data which are stored in the form of singularly isolated, discontinuous data or digits.
In one aspect of the invention, a method is implemented to provide a correct by construction capacitor array in a manner that significantly reduces design cycle time and resolves difficulties associated with quality checking of the array and providing parasitic information in user friendly way, by integrating all of the tasks that are necessary for manual generation of a capacitor array.
In still another aspect of the invention, a method is implemented to provide a correct by construction capacitor array in a manner that functions with a minimum number of inputs.
In yet another aspect of the invention, a method is provided to implement a correct by construction capacitor array in a manner that requires only a capacitor array map.
In another aspect of the invention, a method is provided to implement a correct by construction capacitor array in a manner that automatically generates other inputs with the help of a user provided capacitor array map.
In still another aspect of the invention, a method is provided that allows use of design rules for different processes to allow capacitor array tailoring specific to each design.
In yet another aspect of the invention, a method is provided to eliminate design rule errors in capacitor array layout to facilitate manufacturability requirements.
In another aspect of the invention, a method allows multiple integrated circuit capacitor arrays to be optimized for different purposes to preserve silicon area.
In still another aspect of the invention, a method allows fast and easy migration of a capacitor array layout from one process to another.
One embodiment of the present method most preferably is implemented using algorithmic software such that a data processing device can operate on user supplied discrete data including capacitor array design rules, a capacitor array map file, custom (user specified) rules, and unit capacitor cell x and y active area dimensions to:
generate a unit capacitor cell;
generate a master data file;
place a plurality of unit capacitor cells in array fashion according to unit capacitor cell data and the master data file;
map group numbers associated with the unit capacitor cells in each row to virtual numbers;
determine bottom capacitor plate connectivity requirements via the mapped virtual numbers; and
determine top capacitor plate connectivity requirements.